Digital Design and Computer Architecture - Lecture 10a: Instruction Set Architecture

This post is a derivative of Digital Design and Computer Architecture Lecture by Prof. Onur Mutlu, used under CC BY-NC-SA 4.0.

You can watch this lecture on Youtube and see pdf.

I write this summary for personal learning purposes.

Intro

Agenda for Today & Next Few Lectures

• LC-3 and MIPS Instruction Set Architectures
• LC-3 and MIPS assembly and programming
• Introduction to microarchitecture and single-cycle microarchitecture
• Multi-cycle microarchitecture

Required Readings

• Von Neumann Model, LC-3, and MIPS
  • P&P, Chapters 4, 5
  • H&H, Chapter 6
  • P&P, Appendices A and C (ISA and microarchitecture of LC-3)
  • H&H, Appendix B (MIPS instructions)
• Programming
  • P&P, Chapter 6
  • Recommended: H&H Chapter 5, especially 5.1, 5.2, 5.4, 5.5

Recall: The Instruction Cycle

• FETCH
• DECODE
• EVALUATE ADDRESS
• FETCH OPERANDS
• EXECUTE
• STORE RESULT

Instruction Set Architecture

The ISA is the interface between what the software commands and what the hardware carries out.

The ISA specifies

• The memory organization

  • Address space (LC-3: 2^16, MIPS: 2^32)
  • Addressability (LC-3: 16 bits, MIPS: 32 bits)
  • Word- or Byte-addressable

• The register set

  • R0 to R7 in LC-3
  • 32 registers in MIPS

• The instruction set

  • Opcodes

  • Data types

    • An ISA supports one or several data types

    • LC-3 only supports 2’s complement integers

      • Negative of a 2’s complement binary value X = NOT(X) + 1

    • MIPS supports

      • 2’s complement integers
      • Unsigned integers
      • Floating point

    • Tradeoffs

      • Think compiler/programmer vs. microarchitect

      • Concept of semantic gap

        • Data types coupled tightly to the semantic level, or complexity

          of instructions

  • Addressing modes

    • An addressing mode is a mechanism for specifying where an operand is located

Operate Instructions

In LC-3, there are three operate instructions

• NOT is a unary operation (one source operand)
  • It executes bitwise NOT
• ADD and AND are binary operations (two source operands)
  • ADD is 2’s complement addition
  • AND is bitwise SR1 & SR2

In MIPS, there are many more

• Most of R-type instructions (they are binary operations)
  • E.g., add, and, nor, xor…
• I-type versions (i.e., with one immediate operand) of the R-type operate instruction
• F-type operations, i.e., floating-point operations

Data Movement Instructions and Addressing Modes

In LC-3, there are seven data movement instructions

• LD, LDR, LDI, LEA, ST, STR, STI

• Format of load and store instructions

  • Opcode (bits [15:12])

  • DR or SR (bits [11:9])

  • Address generation bits (bits [8:0])

  • Four ways to interpret bits, called addressing modes

    • PC-Relative Mode (LD and ST)
    • Indirect Mode (LDI and STI)
    • Base+offset Mode (LDR and STR)
    • Immediate Mode (LEA)

In MIPS, there are only Base+offset and immediate modes for load and store instructions.

Control Flow Instructions

• Allow a program to execute out of sequence
• Conditional branches and jumps
  • Conditional branches are used to make decisions (E.g., if-else statement)
  • In LC-3, three condition codes are used
  • Jumps are used to implement
    • Loops
    • Function calls
  • JMP in LC-3 and j in MIPS

Condition Codes in LC-3

Each time one GPR (R0-R7) is written, three single-bit registers are updated. Each of these condition codes are either set (set to 1) or cleared (set to 0).

• If the written value is negative, N is set, Z and P are cleared.
• If the written value is zero, Z is set, N and P are cleared.
• If the written value is positive, P is set, N and Z are cleared.

Lecture Summary

• Instruction Set Architectures: LC-3 and MIPS
  • Operate instructions
  • Data movement instructions
  • Control instructions
• Instruction formats
• Addressing modes